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PLL DIVIDER/MULITPLIER SELECTION

CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

Table 1. Input-to-Output Settings

INPUT FRE-

OUTPUT FRE-

PREDIVIDER

POST DIVIDER

INPUT-TO-OUTPUT MULTIPLI-

QUENCY (MHz)

QUENCY (MHz)

NOTE

CATION-RATIO

FROM

TO

FROM

TO

MULT0

MULT1

P0

P1

P2

8

12.5

35

100

280

1

0

1

1

12.5

39

50

156

1

0

1

0

4

25

70

100

280

1

1

1

1

12.5

39

25

78

1

0

0

1

2

25

78

50

156

1

1

0

1

0

50

140

100

280

0

0

1

1

25

78

25

78

1

1

0

1

1

50

156

50

156

0

0

1

0

100

240

100

240

0

1

1

1

CLKOUT high-impedance

X

X

0

0

CLOUOTB high-impedance

CLKOUT = high

X

X

1

0

1

Special mode of operation

CLKOUTB = high

CLKOUT = P2

X

X

1

X

CLKOUTB = P2

(1)

There is some overlapping of the input frequency ranges for multiplication ratios of 1, 2, and 4. For example, an input frequency of 30

MHz for a multiplication ratio of four falls within both the 12.5 to 39-MHz range and the 25 to 70-MHz range. For best device operation in

a case such as this, always select the input frequency range nearer to the top of the table.

Table 2. Power Down Modes

STATE

PWRDNB

STOPB

CLKOUT and CLKOUTB

Power down

0

X

GNDO

Clock stop

1

0

Normal

1

1

See Table 1

Table 3. Programmable Delay and Phase Alignment

DLYCTR

NOTE

LEADLAG

CLKOUT and CLKOUTB

Advanced by one step:

For every 32 edges, there are one or two

Each rising

step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11

HI

edges for which the phase aligner does not

edge+

1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10

update the phase. Therefore, CLKOUT

1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01

Delayed by one step:

The frequency of the DLYCTRL pin should

Each rising

step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11

always be equal to or less than the

LO

edge+

1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10

frequency of the LEADLAG pin.

1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01

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