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CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

CLKOUT

2018

O

Output CLK signal (low-noise CMOS) Complementary output CLK signal (low-noise CMOS)

CLKOUTB

DLYCTRL

7

I

CLKOUT/CLKOUTB period (1.3 mUI). (E.g., for a 90-degree delay or advancement one needs to

provide 192 rising edges). See Table 3.

GND

5

GND for VDDREF and VDDPD

GNDO

17, 21

GND for the output pins (CLKOUT, CLKOUTB)

GNDP

4

GND for the PLL

GNDPA

8

GND for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB, PWRDNB

LEADLAG

6

I

Controls whether the output CLK is delayed or advanced relative to REFCLK. See Table 3.

MULT0

15

I

PLL multiplication factor select. See Table 1.

MULT1

14

MULT[0:1] = 10:

×16

MULT[0:1] = 11:

×8

MULT[0:1] = 00:

×4

MULT[0:1] = 01:

×2

NC

19

Not connected; leave pin floating or tied to GND.

P0

24

I

Mode control pins (see Table 1)

0 - Normal operation

1 - High-Z outputs and other special settings

P1

23

I

Post divider control (see Table 1)

P[1:2] = 11: div2

P[1:2] = 10: div4

P2

13

P[1:2] = 01: div8

PWRDNB

12

I

Active-low power-down state. CLKOUT/CLKOUTB goes low, See Table 2).

0 - IC in power down

1 - Normal operation

REFCLK

2

I

Reference input clock

STOPB

11

I

Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as

listed in Table 2.

0 - Outputs disabled

1 - Normal operation

VDDO

16, 22

VDD for the output pin (CLKOUT, CLKOUTB) and power down circuit

VDDP

3

VDD for PLL and input buffer

VDDPA

9

VDD for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], and STOPB

VDDPD

10

Reference voltage for inputs LEADLAG and DLYCTRL

VDDREF

1

Reference voltage for REFCLK

4