CDCF5801 datasheet(7/17 Pages) TI

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ELECTRICAL CHARACTERISTICS

VDDO

) 0.2

VDDO

*0.2

CDCF5801

SCAS698D – SEPTEMBER 2003 – REVISED DECEMBER 2004

TIMING REQUIREMENTS (continued)

PARAMETER

MIN

MAX

UNIT

Allowable frequency on LEADLAG

280

MHz

Allowable duty cycle on DLYCTRL and LEADLAG pins

25%

75%

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS(1)

MIN TYP(2)

MAX

UNIT

VO(STOP)

Output voltage during Clkstop mode

See Figure 1

1.1

VO(X)

Output crossing-point voltage

See Figure 1 and Figure 4

Output voltage swing (VOH - VOL)

See Figure 1

1.7

2.9

VIK

Input clamp voltage

VDD = 3 V,

II = -18 mA

-1.2

VDD = 3 to 3.6 V,

See Figure 1

2.5

VOH

High-level output voltage

VDD = 3 V,

IOH = -16 mA

2.2

VDD = 3 to 3.6 V,

See Figure 1

0.4

0.6

VOL

Low-level output voltage

VDD = 3 V,

IOH = 16 mA

0.5

VDD = 3.135 V,

VO = 1 V

-32

-52

IOH

High-level output current

VDD = 3.3 V,

VO = 1.65 V

-51

VDD = 3.465 V,

VO = 3.135 V

-14.5

-21

VDD = 3.135 V,

VO = 1.95 V

61.5

IOL

Low-level output current

VDD = 3.3 V,

VO = 1.65 V

VDD = 3.465 V,

VO = 0.4 V

25.5

IOZ

High-impedance-state output current

P0 = 1,

P1 = P2 = 0

±10

µA

High-impedance-state output current

IOZ(STOP)

Stop = 0,

VO = GND or VDD

±100

µA

during Clk Stop

High-impedance-state output current

IOZ(PD)

PWRDNB = 0,

VO = GND or VDD

-10

100

µA

in power-down state

IIH

REFCLK; STOPB;

VDD = 3.6 V,

VI = VDD

µA

High-level

PWRDNB; P[0:2];

input current

MULT[0:1];

IIL

VDD = 3.6 V,

VI =0

-10

µA

DLYCTRL; LEADLAG

Output

High state

RI at IO-14.5 mA to -16.5 mA

impedance

Ω

(single

Low state

RI at IO 14.5 mA to 16.5 mA

ended)

PWRDNB = 0

µA

Reference

IREF

VDDREF; VDDPD

VDD = 3.6 V

current

PWRDNB = 1

0.5

Input capacitance

VI = VDD or GND

Output capacitance

VO = GND or VDD

REFCLK = 0 MHz to 280 MHz;

IDD(PD)

Supply current in power-down state

PWRDNB = 0; STOPB = 1

IDD(CLKSTOP) Supply current in CLK stop state

BUSCLK configured for 280 MHz

Supply current (normal operation

BUSCLK 280 MHz, MULT[0:1] = 10;

IDD(NORMAL)

mode)

P[0:2] = 011; Load , See Figure 1

(1)

VDD refers to any of the following; VDDP, VDDREF, VDDO, VDDPD, and VDDPA

(2)

All typical values are at VDD = 3.3 V, TA = 25°C.

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