TMS320VC5471GHKA datasheet(73/97 Pages) TI

73 / 97 page

Electrical Specifications

June 2001 – Revised December 2002

SPRS180C

6.11 Multichannel Buffered Serial Port (McBSP) Timings

6.11.1

McBSP Receive and Transmit Timings

Table 6–16 and Table 6–17 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 6–16 and Figure 6–17).

NOTE: Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals

is inverted, then the timing references of that signal are also inverted.

Table 6–16. McBSP Receive and Transmit Timing Requirements

MIN

MAX

UNIT

tc(BCKRX)

Cycle time, BCLK_R/X

BCLK_R/X ext

tw(BCKRX)

Pulse duration, BCLK_R/X or BCLK_R/X high

BCLK_R/X ext

2H–1

Hold time external BFSR high after BCLKR low

BCLKR int

th(BCKRL-BFRH)

Hold time, external BFSR high after BCLKR low

BCLKR ext

Hold time BDR valid after BCLKR low

BCLKR int

th(BCKRL-BDRV)

Hold time, BDR valid after BCLKR low

BCLKR ext

Hold time external BFSX high after BCLKX low

BCLKX int

th(BCKXL-BFXH)

Hold time, external BFSX high after BCLKX low

BCLKX ext

Setup time external BFSR high before BCLKR low

BCLKR int

tsu(BFRH-BCKRL)

Setup time, external BFSR high before BCLKR low

BCLKR ext

Setup time BDR valid before BCLKR low

BCLKR int

tsu(BDRV-BCKRL)

Setup time, BDR valid before BCLKR low

BCLKR ext

Setup time external BFSX high before BCLKX low

BCLKX int

tsu(BFXH-BCKXL)

Setup time, external BFSX high before BCLKX low

BCLKX ext

tr(BCKRX)

Rise time, BCLKR_R/X

BCLK_R/X ext

tf(BCKRX)

Fall time, BCLKR_R/X

BCLK_R/X ext

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