LTC2413IGN datasheet(14/44 Pages) LINER

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LTC2413

sn2413 2413fs

on the rising edge of the 32nd SCK pulse. On the falling

edge of the 32nd SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

As long as the voltage on the IN+ and IN– pins is maintained

within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

Simultaneous Frequency Rejection

The LTC2413 internal oscillator provides better than 87dB

normal mode rejection over the range of 49Hz to 61.2Hz as

shown in Figure 4. For this simultaneous 50Hz/60Hz

rejection, FO should be connected to GND.

When a fundamental rejection frequency different from

the range 49Hz to 61.2Hz is required or when the converter

must be sychronized with an outside source, the LTC2413

can operate with an external conversion clock. The conveter

automatically detects the presence of an external clock

signal at the FO pin and turns off the internal oscillator. The

frequency fEOSC of the external signal must be at least

2560Hz to be detected. The external clock signal duty cycle

is not significant as long as the minimum and maximum

specifications for the high and low periods, tHEO and tLEO,

are observed.

Table 2. LTC2413 Output Data Format

Differential Input Voltage

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

…

Bit 0

VIN*

EOC

DMY

SIG

MSB

VIN* ≥ 0.5 • VREF**

0110

…

0.5 • VREF** – 1LSB

0101

…

0.25 • VREF**

0101

…

0.25 • VREF** – 1LSB

0100

…

0100

…

–1LSB

0011

…

– 0.25 • VREF**

0011

…

– 0.25 • VREF** – 1LSB

0010

…

– 0.5 • VREF**

0010

…

VIN* < –0.5 • VREF**

0001

…

*The differential input voltage VIN = IN+ – IN–.

**The differential reference voltage VREF = REF+ – REF–.

Figure 3. Output Data Timing

APPLICATIO S I FOR ATIO

MSB

SIG

“0”

262732

BIT 0

BIT 27

BIT 5

LSB24

BIT 28

BIT 29

BIT 30

SDO

SCK

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

2413 F03

Hi-Z

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