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LTC2413IGN bảng dữ liệu(PDF) 11 Page - Linear Technology

tên linh kiện LTC2413IGN
Giải thích chi tiết về linh kiện  24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection
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nhà sản xuất  LINER [Linear Technology]
Trang chủ  http://www.linear.com
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LTC2413IGN bảng dữ liệu(HTML) 11 Page - Linear Technology

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LTC2413
11
sn2413 2413fs
TEST CIRCUITS
APPLICATIO S I FOR ATIO
FU CTIO AL BLOCK DIAGRA
Figure 2. LTC2413 State Transition Diagram
CONVERTER OPERATION
Converter Operation Cycle
The LTC2413 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 2). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2413 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫
∫
∫
GND
VCC
IN+
IN–
SDO
SCK
REF+
REF –
CS
FO
(INT/EXT)
2413 FD
–+
+
–
1.69k
SDO
2413 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
1.69k
SDO
2413 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
CONVERT
SLEEP
DATA OUTPUT
2413 F02
TRUE
FALSE
CS = LOW
AND
SCK
Figure 1. Functional Block Diagram



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