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KESTX01MPAS bảng dữ liệu(PDF) 3 Page - Zarlink Semiconductor Inc |
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KESTX01MPAS bảng dữ liệu(HTML) 3 Page - Zarlink Semiconductor Inc |
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3 / 10 page ![]() 2 KESTX01 ELECTRICAL CHARACTERISTICS Operating conditions T amb = –40 °C to + 85°C, V CC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Value Units Conditions Min Typ Max Power supply voltage V CC 3.5 6.5 V Ambient temperature Ta –40 +85 °C Electro static discharge 2kV all pins – human body model ELECTRICAL CHARACTERISTICS D.C. T amb = –40 °C to + 85°C, V CC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Value Units Condition Min Typ Max Supply current I CC1 0.7 µAV TXEN =0V; V DATA =0V;Ta=25°C stand by mode V CC = 7V Supply current I CC 2 1.6 2.8 4 mA I mod =0 µA; VCC =V TXEN 3.5V PLL enable/transmit space V DATA =LOW; 434MHz Supply current I CC 3 6.4 8.5 10.1 mA I mod =150 µA; VCC =V TXEN =3.5V PLL enable/transmit mark V DATA =HIGH; 434MHz Supply current I CC 4 1.6 3.17 5.0 mA I mod =0 µA; VCC =V TXEN =6.5V PLL enable/transmit space V DATA =LOW; 434MHz Supply current I CC 5 6.4 9.8 12.5 mA I mod =150 µA; V CC =V TXEN =6.5V PLL enable/transmit mark V DATA =HIGH; 434MHz see note 1 TXEN – transmit enable Ven 3.5 V CC +0.2 V TXEN – transmit V dis V EE –0.2 0.5 V disable/stand by Input bias current TXEN I txen 150 µA TXEN = V CC transmit enable Bias voltage pin PWRC 1.0 1.20 1.5 V I mod =150 A V CC = 3.5V Data pin input logic high V ih 0.7V CC V CC +0.5 V Data pin input logic low V il V EE –0.5 0.3V CC V Data pin input current – I inl –100 µAV CC = 7V logic low V DATA = 2.1V Data pin input current – I inh +100 µAV CC = 7V logic high V DATA = 4.9V Notes:– 1. The maximum supply current is directly related to Imod and hence the output power level. (Figure 4) |
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