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KESTX01MPAS bảng dữ liệu(PDF) 8 Page - Zarlink Semiconductor Inc |
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KESTX01MPAS bảng dữ liệu(HTML) 8 Page - Zarlink Semiconductor Inc |
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8 / 10 page ![]() 7 KESTX01 y) p OP OPb XTAL2 XTAL1 Rs CLK C COMPONENT LIST at 433.92MHz COMPONENTS FUNCTION VALUE UNITS R1 OUTPUT POWER CONTROL 2.0 k Ω R2 PLL LOOP FILTER 4.7 k Ω C1 ANTENNA TUNING APPLICATION pF DEPENDENT L1 and L2 ANTENNA TUNING APPLICATION nH DEPENDENT C2 PLL LOOP FILTER 220 pF C3 PLL LOOP FILTER 10 nF X1 PARALLEL RESONANT CRYSTAL 6.78 MHz C4 CRYSTAL OSCILLATOR 18 pF C5 CRYSTAL OSCILLATOR 18 pF Note: The value of C1 is split between two capacitors to aid in balancing the antenna loop reducing the level of the second harmonic TESTABILITY REQUIREMENTS This section is a summary of the observability and control- lability requirements identified to simplify the production test requirements of the device. 1. Ability to directly drive the XTAL oscillator from the tester (no crystal). The XTAL2 pin allows direct drive of the oscillator with an external clock source as shown in Figure 7. Typically a 200mVpk clock signal is AC coupled to produce differential output on OP and OPb. (C=10nF, R s (Source) <5k Ω) Figure 7 Direct drive of crystal oscillator 2. Control of the VCO frequency is obtained via the LF1 signal pin. The output of the dividers is tested by measuring the DC current output of the charge pump (with XTAL2 held at V CC ). 3. DC operation of the power amplifier is observed by measuring the current through the open collector outputs OUT and OUTB. The VCO input to the power amplifier is disabled with VCOTST tied to V CC and the bias current being measured with DATA tied to V CC . Toggling DATA input will modulate the bias current in the power amplifier. |
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