HM628128ALP-7SL datasheet(12/13 Pages) HITACHI

tên linh kiện	HM628128ALP-7SL

Giải thích chi tiết về linh kiện	131,072-word X 8-bit High Speed CMOS Static RAM

PDF	13 Pages

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nhà sản xuất	HITACHI [Hitachi Semiconductor]

Trang chủ	http://www.renesas.com/eng

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12 / 13 page

data bus contention.

tWP ≥ tDW min + tWHZ max

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions*4

VCC for data retention

VDR

2.0

—

CS1

≥ VCC – 0.2 V,

CS2

≥ VCC – 0.2 V or

0 V

≤ CS2 ≤ 0.2 V

Vin>0 V

Data retention current

ICCDR

—1

50*1

µA

VCC = 3.0 V, Vin ≥ 0 V

(L version)

CS1

≥ VCC – 0.2V

ICCDR

—1

30*2

µA

CS2

≥ VCC – 0.2 V or

(L-L version)

0 V

≤ CS2 ≤ 0.2 V

ICCDR

—1

15*3

µA

(L-SL

version)

Chip deselect to

tCDR

—

See retention waveform

data retention time

Operation recovery time

5—

—

Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)

Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)

HM628128A Series

4.5 V

2.2 V

0 V

CS1

tCDR

CS1

– 0.2 V

DR1

Data retention mode

4.5 V

0 V

CS2

CDR

0 V

CS2

0.2 V

DR2

Data retention mode

0.4 V

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