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AD12400

Rev. 0 | Page 19 of 28

AD12400 EVALUATION KIT

The AD12400/KIT offers an easy way to evaluate the AD12400.

The AD12400/KIT includes the AD12400KWS mounted on an

adapter card, the AD12400 evaluation board, the power supply

cables, a 225 MHz Buffer Memory FIFO board, and the Dual

Analyzer software. The user must supply a clock source, an

analog input source, a 1.5 V power supply, a 3.3 V power supply,

a 5 V power supply, and a 3.8 V power supply. The clock source

and analog input source connect directly to the AD12400KWS.

The power supply cables (included) and a parallel port cable

(not included) connect to the evaluation board.

Power Connector

Power is supplied to the board via a detachable 12-lead power

strip (three 4 pin blocks).

Table 8. Power Connector

VA 3.8 V

Analog supply for the ADC (950 mA typical)

VC 3.3 V

Digital supply for the ADC outputs (200 mA

typical)

VD 1.5 V*

Digital supply for the FPGA (2.5 A max, 1.4 A

typical)

VB 5.0 V

Digital supply for the Buffer memory board

(400 mA typical)

*The power supply cable has approximately 100 mV drop.

The VD supply current is dependent upon the analog input

frequency. Refer to Figure 17.

Analog Input

The analog input source connects directly to an SMA on the

AD12400KWS.

Encode

The single-ended or differential encode signal connects directly

to SMA connector(s) on the AD12400KWS. A single-ended

sine wave at 10 dBm connected to the Encode SMA is recom-

mended. A low jitter clock source is recommended (<0.5 ps) to

properly evaluate the AD12400.

Data Outputs

The AD12400KWS digital outputs are available at the 80-pin

connector, P2, on the evaluation board. The AD12400/KIT

comes with a Buffer Memory FIFO board connected to P2

that provides the interface to the parallel port of a PC. The

Dual Analyzer software is compatible with Windows® 95,

Windows® 98, Windows® 2000, and Windows NT®.

The Buffer Memory FIFO board can be removed and an

external logic analyzer, or other data acquisition module, can be

connected to this connector if required.

Adapter Card

The AD12400KWS is attached to an adapter card that interfaces

to the evaluation board through a 120-pin connector, P1, which

is on the top side of the evaluation board.

Digital Post Processing Control

The AD12400 has a two-pin jumper labeled AFB that allows the

user to enable/disable the digital post processing. The digital

post processing is active when the AFB jumper is applied. When

the jumper is removed, the FPGA is set to a pass through mode,

which will demonstrate to the user the performance of the

AD12400 without the digital post processing.

RESET

The AD12400KWS’s FPGA configuration is stored in an

EEPROM and loaded into the FPGA when power is applied to

the AD12400. The RESET switch, SW1 (active low), allows the

user to reload the FPGA in case of a low voltage condition or a

power supply glitch. Depressing the RESET switch will pull the

data ready and output bits high. The RESET switch should

remain low for a minimum of 200 ns. On the rising edge of the

RESET pulse, the AD12400 will start loading the configuration

into the on-module FPGA. The reload process requires a

maximum of 600 ms to complete. Valid signals on the data-

ready pins indicate that the reset process is complete.

The AD12400 is not compatible with the HSC-ADC-EVAL-

DC/SC hardware or software.

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