AD12400SLASHKIT datasheet(16/28 Pages) AD

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AD12400

Rev. 0 | Page 16 of 28

ANALOG INPUT

The AD12400 analog input is ac-coupled using a proprietary,

transformer front end circuit that provides 1 dB of gain flatness

over the first Nyquist zone and a –3 dB bandwidth of 450 MHz.

This front end circuit provides a VSWR of 1.5 (50 Ω) over the

first Nyquist zone, and the typical full-scale input is 3.2 V p-p

The MiniCircuits HELA-10 amplifier module can be used to

drive the input at these power levels.

CLOCK INPUT

The AD12400 requires a 400 MSPS encode that is divided by 2

and distributed to each ADC channel, 180° out of phase from

each other. Internal ac-coupling and bias networks provide the

framework for flexible clock input requirements that include

single-ended sine-wave, single-ended PECL, and differential

PECL. While the AD12400 is tested and calibrated using a

single-ended sine-wave, properly designed PECL circuits that

provide fast slew rates (>1V/ns) and minimize ringing will

result in comparable dynamic range performance.

There are two major factors to consider when designing the

input clock circuit for the AD12400: aperture jitter and

harmonic content. The relationship between aperture jitter and

SNR can be characterized using the following equation. The

equation assumes a single-tone full-scale input signal.

(

)

(LSB

noise

input

ADC

(LSB)

DNL

ADC

(bits)

resolution

ADC

jitter

Aperture

frequency

Input

log

rms

NOISE

JRMS

SNR

NOISErms

JRMS

−

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎟

⎠

⎞

⎜⎜

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

Figure 20 displays the application of this relationship to full-

scale, single-tone input signal on the AD12400, where the DNL

was assumed to be 0.4 LSB, and the input noise was assumed to

be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR at

the jitter level present in the AD12400 evaluation system,

including the jitter associated with the AD12400 itself.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

APERTURE JITTER (ps rms)

AIN = 10MHz

AIN = 65MHz

AIN = 128MHz

AIN = 180MHz

Figure 20. SNR vs. Aperture Jitter

In addition to jitter, the harmonic content of single-ended sine

wave clock sources must be controlled as well. The clock source

used in the test and calibration process has a harmonic

performance that is better than 60 dBc. Also, when using PECL

or other square-wave clock sources, unstable behavior such as

overshoot and ringing can affect phase matching and degrade

the image spur performance

DIGITAL OUTPUTS

The AD12400’s digital post processing circuit provides two

parallel, 12-bit 200 MSPS data output buses. By providing two

output busses that operate at one half the conversion rate, the

AD12400 eliminates the need for large, expensive, high power

demultiplexing circuits. The output data format is twos

complement, maintaining the standard set by other high speed

A/D converters such as the AD9430 and AD6645. Data-ready

signals are provided for facilitating proper timing in the data

capture circuit. Finally, the digital post processing circuit can be

configured to provide alternate data output formats. Contact the

factory for more details.

POWER SUPPLIES

The AD12400 requires three different supply voltages: a 1.5 V

supply for the digital post processing circuit, a 3.3 V supply to

facilitate digital I/O through the system, and a 3.8 V supply for

the analog conversion and clock distribution circuits. The

AD12400 incorporates two key features that result in solid

power supply rejection ratio (PSRR) performance. First, on-

board linear regulators are used to provide an extra level of

power supply rejection for the analog circuits. The linear

regulator used to supply the A/D converters provides an

additional 60 dB of rejection at 100 kHz. Second, in order to

address higher frequency noise (where the linear regulators’

rejection degrades), the AD12400 incorporates high quality

ceramic decoupling capacitors.

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