V850ESLASHMA2 datasheet(8/226 Pages) NEC

8 / 226 page

User’s Manual U14559EJ3V1UM

CONTENTS

CHAPTER 1 GENERAL........................................................................................................................... 12

1.1

Features......................................................................................................................................... 13

1.2

Internal Configuration .................................................................................................................. 14

CHAPTER 2 REGISTER SET................................................................................................................. 15

2.1

Program Registers ....................................................................................................................... 16

2.2

System Registers ......................................................................................................................... 18

2.2.1

Interrupt status saving registers (EIPC, EIPSW)................................................................................ 19

2.2.2

NMI status saving registers (FEPC, FEPSW) .................................................................................... 20

2.2.3

Exception cause register (ECR) ......................................................................................................... 20

2.2.4

Program status word (PSW) .............................................................................................................. 21

2.2.5

CALLT caller status saving registers (CTPC, CTPSW)...................................................................... 23

2.2.6

Exception/debug trap status saving registers (DBPC, DBPSW) ........................................................ 24

2.2.7

CALLT base pointer (CTBP) .............................................................................................................. 25

2.2.8

Debug interface register (DIR) ........................................................................................................... 26

2.2.9

Breakpoint control registers 0 and 1 (BPC0, BPC1)........................................................................... 29

2.2.10 Program ID register (ASID) ................................................................................................................ 30

2.2.11 Breakpoint address setting registers 0 and 1 (BPAV0, BPAV1)......................................................... 31

2.2.12 Breakpoint address mask registers 0 and 1 (BPAM0, BPAM1) ......................................................... 31

2.2.13 Breakpoint data setting registers 0 and 1 (BPDV0, BPDV1) .............................................................. 32

2.2.14 Breakpoint data mask registers 0 and 1 (BPDM0, BPDM1) ............................................................... 32

CHAPTER 3 DATA TYPES .................................................................................................................... 33

3.1

Data Format................................................................................................................................... 33

3.2

Data Representation..................................................................................................................... 35

3.2.1

Integer................................................................................................................................................ 35

3.2.2

Unsigned integer ................................................................................................................................ 35

3.2.3

Bit....................................................................................................................................................... 35

3.3

Data Alignment ............................................................................................................................. 36

CHAPTER 4 ADDRESS SPACE ............................................................................................................ 37

4.1

Memory Map.................................................................................................................................. 38

4.2

Addressing Mode ......................................................................................................................... 39

4.2.1

Instruction address............................................................................................................................. 39

4.2.2

Operand address ............................................................................................................................... 41

CHAPTER 5 INSTRUCTIONS ................................................................................................................. 43

5.1

Instruction Format ........................................................................................................................ 43

5.2

Outline of Instructions ................................................................................................................. 47

5.3

Instruction Set............................................................................................................................... 51

ADD ............................................................................................................................................................... 53

ADDI .............................................................................................................................................................. 54

AND ............................................................................................................................................................... 55

ANDI .............................................................................................................................................................. 56

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