AR0230CS datasheet(5/24 Pages) ONSEMI

5 / 24 page

AR0230CS

www.onsemi.com

PIXCLK

LINE_VALID

FRAME_VALID

FLASH

SHUTTER

SADDR

SDATA

SCLK

TRIGGER

OE_BAR

TEST

EXTCLK

DGND

AGND

VDD_IO

VDD

VDD_PLL

VAA

VAA_PIX

From

controller

Master clock

(6−48 MHz)

Digital

I/O

power

Digital

Core

power

PLL

power

Analog

power

Analog

power

RESET_BAR

Digital

ground

Analog

ground

controller

NOTES:

VDD_IO

VDD

VDD_PLL VAA

VAA_PIX

VDD_IO

DOUT[11:0]

Figure 3. Typical Configuration: Serial Four−Lane HiSPi Interface

7. All power supplies must be adequately decoupled.

8. ON Semiconductor recommends a resistor value of 1.5k

Ω, but a greater value may be used for

slower two−wired speed.

9. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output

interface is used.

10. ON Semiconductor recommends that 0.1

μF and 10 μF decoupling capacitors for each power

supply are mounted as close as possible to the pad. Actual values and results may vary

depending on lay out and design considerations. Refer to the AR0230CS demo headboard

schematics for circuit recommendations.

11. ON Semiconductor recommends that analog power planes are placed in a manner such that

coupling with the digital power planes is minimized.

12. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage

currents.

13. The EXTCLK input is limited to 6−48 MHz

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