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WM8976 bảng dữ liệu(PDF) 20 Page - Wolfson Microelectronics plc

tên linh kiện WM8976
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WM8976
Preliminary Technical Data
w
PTD Rev 2.0 February 2005
20
Figure 10 DAC Power Up and Down Sequence (not to scale)
SYMBOL
MIN
TYPICAL
MAX
UNIT
tline_midrail_on
60
ms
tline_midrail_off
6
s
thp_midrail_on
150
ms
thp__midrail_off
9
s
tdacint
2/fs
n/fs
DAC Group Delay
29/fs
n/fs
Table 4 Typical DAC Power Up and Down Sequence
Notes:
1.
The lineout charge time, tline_midrail_on, is mainly determined by the VMID pin charge time. This
time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance
and AVDD power supply rise time. The values above were measured using a 1µF capacitor and
were taken at 10% and 90% points on the charge time curve.
2.
It is not advisable to allow DACDAT data input during initialisation of the DAC. If the DAC data
value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue
outputs. The same is also true if the DACDAT is removed at a none zero value, and no mute
function has been applied to the signal beforehand.
3.
The lineout discharge time, tline_midrail_off, is dependent upon the value of the lineout coupling
capacitor and the leakage resistance path to ground. The values above were measured using a
1µF capacitor and were taken at 10% and 90% points on the discharge time curve.



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