TUSB546AI-DCI datasheet(17/49 Pages) TI1

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TUSB546A-DCI

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SLLSF14 – JUNE 2017

Product Folder Links: TUSB546A-DCI

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NOTE

All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal

pull-up and pull-down resistors will be isolated in order to save power.

8.3.4 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in

the system before the input of the TUSB546A-DCI. The receiver overcomes these losses by attenuating the low

frequency components of the signals with respect to the high frequency components. The proper gain setting

should be selected to match the channel insertion loss before the input of the TUSB546A-DCI receivers. Two 4-

level inputs pins enable up to 16 possible equalization settings. USB3.1 upstream path, USB3.1 downstream

path, and DisplayPort each have their own two 4-level inputs. The TUSB546A-DCI also provides the flexibility of

adjusting settings through I2C registers.

8.4 Device Functional Modes

8.4.1 Device Configuration in GPIO Mode

The TUSB546A-DCI is in GPIO configuration when I2C_EN = “0”. The TUSB546A-DCI supports the following

configurations: USB 3.1 only, 2 DisplayPort lanes + USB 3.1, or 4 DisplayPort lanes (no USB 3.1). The CTL1 pin

controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.1 only, 2

lanes of DisplayPort, or 4-lanes of DisplayPort as detailed in Table 2. The AUXp or AUXn to SBU1 or SBU2

mapping is controlled based on Table 3.

After power-up (VCC from 0 V to 3.3 V), the TUSB546A-DCI defaults to USB3.1 mode. The USB PD controller

upon detecting no device attached to Type-C port or USB3.1 operation not required by attached device must

take TUSB546A-DCI out of USB3.1 mode by transitioning the CTL0 pin from L to H and back to L.

Table 2. GPIO Configuration Control

CTL1 PIN

CTL0 PIN

FLIP PIN

TUSB546A-DCI CONFIGURATION

VESA DisplayPort ALT MODE

DFP_D CONFIGURATION

Power Down

—

Power Down

—

One Port USB 3.1 - No Flip

—

One Port USB 3.1 – With Flip

—

4 Lane DP - No Flip

C and E

4 Lane DP – With Flip

C and E

One Port USB 3.1 + 2 Lane DP- No Flip

D and F

One Port USB 3.1 + 2 Lane DP– With Flip

D and F

Table 3. GPIO AUXp or AUXn to SBU1 or SBU2 Mapping

CTL1 PIN

FLIP PIN

MAPPING

AUXp

→ SBU1

AUXn

→ SBU2

AUXp

→ SBU2

AUXn

→ SBU1

L > 2 ms

Open

Table 4 Details the TUSB546A-DCI’s mux routing. This table is valid for both I2C and GPIO configuration modes.

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