công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

TUSB564 bảng dữ liệu(PDF) 9 Page - Texas Instruments

Click here to check the latest version.
tên linh kiện TUSB564
Giải thích chi tiết về linh kiện  USB TYPE-C DP Alt Mode 8.1 Gbps Sink-Side Linear Redriver Crosspoint Switch
PDF  45 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB564 bảng dữ liệu(HTML) 9 Page - Texas Instruments

Back Button TUSB564 Datasheet HTML 5Page - Texas Instruments TUSB564 Datasheet HTML 6Page - Texas Instruments TUSB564 Datasheet HTML 7Page - Texas Instruments TUSB564 Datasheet HTML 8Page - Texas Instruments TUSB564 Datasheet HTML 9Page - Texas Instruments TUSB564 Datasheet HTML 10Page - Texas Instruments TUSB564 Datasheet HTML 11Page - Texas Instruments TUSB564 Datasheet HTML 12Page - Texas Instruments TUSB564 Datasheet HTML 13Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 45 page
background image
9
TUSB564
www.ti.com
SLLSF29A – OCTOBER 2017 – REVISED OCTOBER 2017
Product Folder Links: TUSB564
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXp/n and SBU1/2
TAUX_PD
Switch propagation delay
1400
ps
TAUX_SW
_OFF
Switching time CTL1 to switch OFF. Not
including TCTL1_DEBOUNCE.
7500
ns
TAUX_SW
_ON
Switching time CTL1 to switch ON
3000
ns
TAUX_INT
RA
Intra-pair output skew
400
ps
USB3.1 and DisplayPort mode transition requirement (GPIO mode)
TGP_USB_
4DP
Min overlap of CTL0 and CTL1 when
transitioning from USB 3.1 only mode to
4-Lane DisplayPort mode or vice versa
4
µs
TCTL1_DE
BOUNCE
CTL1 and HPDIN debounce time when
transitioning from H to L
3
10
ms
I2C (SDA and SCL)
fSCL
I2C clock frequency
1
MHz
tBUF
Bus free time between START and
STOP conditions
0.5
µs
tHDSTA
Hold time after repeated START
condition. After this period, the first clock
pulse is generated
0.26
µs
tLOW
Low period of the I2C clock
0.5
µs
tHIGH
High period of the I2C clock
0.26
µs
tSUSTA
Setup time for a repeated START
condition
0.26
µs
tHDDAT
Data hold time
0
µs
tSUDAT
Data setup time
50
ns
tR
Rise time of both SDA and SCL signals
120
ns
tF
Fall time of both SDA and SCL signals
20 ×
(VI2C/5.5
V)
120
ns
tSUSTO
Setup time for STOP condition
0.26
µs
Cb
Capacitive load for each bus line
100
pF



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com