TUSB564 datasheet(17/45 Pages) TI1

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TUSB564

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SLLSF29A – OCTOBER 2017 – REVISED OCTOBER 2017

Product Folder Links: TUSB564

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8.3 Feature Description

8.3.1 USB 3.1

The TUSB564 supports USB 3.1 Gen 1 datarates up to 5 Gbps. The TUSB564 supports all the USB defined

power states (U0, U1, U2, and U3). Because the TUSB564 is a linear redriver, it can’t decode USB3.1 physical

layer traffic. The TUSB564 monitors the actual physical layer conditions like receiver termination, electrical idle,

LFPS, and SuperSpeed signaling rate to determine the USB power state of the USB 3.1 interface.

The TUSB564 features an intelligent low frequency periodic signaling (LFPS) detector. The LFPS detector

automatically senses the low frequency signals and disables receiver equalization functionality. When not

receiving LFPS, the TUSB564 enables receiver equalization based on the EQ[1:0] and SSEQ[1:0] pins or values

programmed into EQ1_SEL, EQ2_SEL, and SSEQ_SEL registers.

8.3.2 DisplayPort

The TUSB564 supports up to 4 DisplayPort lanes at datarates up to 8.1Gbps (HBR3). The TUSB564, when

configured in DisplayPort mode, monitors the native AUX traffic as it traverses between DisplayPort source and

DisplayPort sink. For the purposes of reducing power, the TUSB564 manages the number of active DisplayPort

lanes based on the content of the AUX transactions. The TUSB564 snoops native AUX writes to DisplayPort

sink’s

DPCD

registers

0x00101

(LANE_COUNT_SET)

and

0x00600

(SET_POWER_STATE).

TUSB564disables/enables lanes based on value written to LANE_COUNT_SET. The TUSB564 disables all lanes

when SET_POWER_STATE is in the D3. Otherwise active lanes will be based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE

various configuration registers.

NOTE

AUX snooping feature is only supported when TUSB564 is configured for I2C mode.

When TUSB564 is configured for GPIO mode, the AUX snoop feature is disabled and all

four DP lanes are enabled if HPDIN is asserted high.

8.3.3 4-level Inputs

The TUSB564 has (I2C_EN, EQ[1:0], DPEQ[1:0], and SSEQ[1:0]) 4-level inputs pins that are used to control the

equalization gain and place TUSB564 into different modes of operation. These 4-level inputs utilize a resistor

divider to help set the 4 valid levels and provide a wider range of control settings. There is an internal 35 k

Ω pull-

up and a 95 k

Ω pull-down. These resistors, together with the external resistor connection combine to achieve the

desired voltage level.

Table 1. 4-Level Control Pin Settings

LEVEL

SETTINGS

Option 1: Tie 1 K

Ω 5% to GND.

Option 2: Tie directly to GND.

Tie 20 K

Ω 5% to GND.

Float (leave pin open)

Option 1: Tie 1 K

Ω 5%to VCC.

Option 2: Tie directly to VCC.

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