AD9289BBC datasheet(20/33 Pages) AD

20 / 33 page

AD9289

Rev. 0 | Page 19 of 32

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift

characteristics. Figure 36 shows the typical drift characteristics

of the internal shared reference in both 1 V and 0.5 V modes.

TEMPERATURE (

°C)

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

–40

–20

VREF = 0.5V

VREF = 1.0V

Figure 36. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT_A and REFT_B and

REFB_A and REFB_B , for the ADC core. The input span is

always twice the value of the reference voltage; therefore, the

external reference must be limited to a maximum of 1 V.

Power and Ground Recommendations

When connecting power to the AD9289, it is recommended that

two separate 3.0 V supplies be used. One for analog (AVDD)

and one for digital (DRVDD). If only one supply is available

then it should be routed to the AVDD first and tapped off and

isolated with a ferrite bead or filter choke with decoupling

capacitors proceeding. One may want to use several different

decoupling capacitors to cover both high and low frequencies.

These should be located close the point of entry at the pc board

level as well as close to the parts with minimal trace length.

A single pc board ground plane should be sufficient when using

the AD9289. With proper decoupling and smart partitioning of

the pc board’s analog, digital, and clock sections, optimum

performance is easily achieved.

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