AD9289

Rev. 0 | Page 5 of 32

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 4.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

CLOCK

Maximum Clock Rate

Full

VI

65

MSPS

Minimum Clock Rate

Full

IV

12

MSPS

Full

VI

6.9

7.7

ns

Full

VI

6.9

7.7

ns

OUTPUT PARAMETERS

Full

IV

0.5

<1.5

CLK cycles

Full

VI

6.9

9.0

11.6

ns

Full

V

250

ps

Full

V

250

ps

Full

V

9.0

ns

Full

V

9.0

ns

Full

VI

±100

±550

ps

Full

VI

±100

±500

ps

Full

IV

±100

±250

ps

25°C

V

1.8

µs

Wake-Up Time

25°C

V

7

ms

Pipeline Latency

Full

IV

6

CLK cycles

APERTURE

25°C

V

4.5

ns

Aperture Uncertainty (Jitter)

25°C

V

<1

ps rms

OUT-OF-RANGE RECOVERY TIME

25°C

V

1

CLK cycles

TIMING DIAGRAMS

LOCK

DCO–

DCO+

D1–

D1+

FCO–

FCO+

CLK–

AIN

CLK+

N-1

N

MSB

(N-7)

D6

(N-7)

D5

(N-7)

D4

(N-7)

D3

(N-7)

D2

(N-7)

D1

(N-7)

LSB

(N-7)

MSB

(N-6)

STATIC

STATIC

STATIC

INVALID

STATIC

STATIC

STATIC

Figure 2. Timing Diagram