AD9289BBC datasheet(15/33 Pages) AD

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AD9289

Rev. 0 | Page 14 of 32

THEORY OF OPERATION

Each A/D converter in the AD9289 architecture consists of a

front send sample-and-hold amplifier (SHA) followed by a

pipe-lined, switched capacitor ADC. The pipelined ADC is

divided into two sections, consisting of six 1.5-bit stages and a

final 2-bit flash. Each stage provides sufficient overlap to correct

for flash errors in the preceding stages. The quantized outputs

from each stage are combined into a final 8-bit result in the

digital correc-tion logic. The pipelined architecture permits the

first stage to operate on a new input sample, while the

remaining stages operate on preceding samples. Sampling

occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor digital-

to-analog converter (DAC) and interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the

reconstructed DAC output and the flash input for the next stage

in the pipeline. One bit of redundancy is used in each of the

stages to facilitate digital correction of flash errors. The last

stage simply consists of a flash ADC.

The input stage contains a differential SHA that can be config-

ured as ac- or dc-coupled in differential or single-ended modes.

The output-staging block aligns the data and carries out the

error correction. The data is serialized and aligned to the frame,

output clock, and lock detection circuitry.

ANALOG INPUT AND REFERENCE OVERVIEW

The analog input to the AD9289 is a differential-switched

capacitor SHA that has been designed for optimum perfor-

mance while processing a differential input signal. The SHA

input can support a wide common-mode range and maintain

excellent performance, as shown in Figure 26 sand Figure 27.

An input common-mode voltage of midsupply minimizes

signal dependent errors and provides optimum performance.

VIN+

VIN–

CPAR

Figure 25. Switched-Capacitor SHA Input UPDATE

The clock signal alternately switches the SHA between sample

mode and hold mode (see Figure 25). When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can

be placed across the inputs to provide dynamic charging

currents. This passive network creates a low-pass filter at the

ADC’s input; therefore, the precise values are dependent on

the application.

The analog inputs of the AD9289 are not internally dc biased. In

ac-coupled applications, the user must provide this bias exter-

nally. Setting the device so that VCM = AVDD/2 is recommended

for optimum performance, but the device functions over a

wider range with reasonable performance (see Figure 26 and

Figure 27).

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

1V p-p, SFDR (dBc)

ANALOG INPUT COMMON-MODE VOLTAGE (V)

0.5

1.0

2.0

1.5

2.5

3.0

Figure 26. SNR, SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz,

fSAMPLE = 65 MSPS

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

1V p-p, SNR (dB)

1V p-p, SFDR (dBc)

ANALOG INPUT COMMON-MODE VOLTAGE (V)

0.5

1.0

2.0

1.5

2.5

3.0

Figure 27. SNR, SFDR vs. Common-Mode Voltage, fIN = 35 MHz,

fSAMPLE = 65 MSPS

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

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