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A8285SLB bảng dữ liệu(PDF) 4 Page - Allegro MicroSystems

tên linh kiện A8285SLB
Giải thích chi tiết về linh kiện  LNB Supply and Control Voltage Regulator
PDF  17 Pages
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nhà sản xuất  ALLEGRO [Allegro MicroSystems]
Trang chủ  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A8285SLB bảng dữ liệu(HTML) 4 Page - Allegro MicroSystems

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Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS
(continued) at T
A = +25°C, VIN = 10 to 16 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Tone Characteristics
Tone Frequency
f
TONE
–
20
22
24
kHz
Tone Pull-Down Current
I
TONE
–30
40
50
mA
Tone Turn-On and Turn-Off Delays
t
DEL
Using EXTM pin
–
–
1
μs
External Tone Logic Input
V
IH
–2
–
–
V
V
IL
–
–
–
0.8
V
Input Leakage
I
IL
––1
–
1
μA
Tone Detector Input Amplitude
V
TDI
f
IN = 22 kHz
260
–
1000
mV
Tone Detector Frequency Capture
f
TDI
600 mV
pp sinewave
17.6
–
26.4
kHz
Tone Detector Input Impedance
Z
TDI
See note 1
–
8.6
–
k
Ω
Tone Detector Output Voltage
V
OL
Tone present, I
LOAD = 3 mA
–
–
0.4
V
Tone Detector Output Leakage
I
OL
Tone absent, V
O = 7 V
–
–
10
μA
I2C Interface
Logic Input (SDA,SCL) Low Level
V
IL
–
–
–
0.8
V
Logic Input (SDA,SCL) High Level
V
IH
–2
–
–
V
Input Hysteresis
V
HYS
–
–
150
–
mV
Logic Input Current
I
IN
V
IN = 0 V to 7 V
–10
<±1.0
10
μA
Output Voltage (SDA, IRQ)
V
OL
I
LOAD = 3 mA
–
–
0.4
V
Output Leakage (SDA, IRQ)
I
OL
V
O = 0 V to 7 V
–
–
10
μA
SCL Clock Frequency
f
CLK
–
0
–
400
kHz
Output Fall Time
t
OF
V
IH to VIL
–
–
250
ns
Bus Free Time Between Stop and Start
t
BUF
See I2C Interface Timing Diagram
1.3
–
–
μs
Hold Time for Start Condition
t
HD:STA
See I2C Interface Timing Diagram
0.6
–
–
μs
Setup Time for Start Condition
t
SU:STA
See I2C Interface Timing Diagram
0.6
–
–
μs
SCL Low Time
t
LOW
See I2C Interface Timing Diagram
1.3
–
–
μs
SCL High Time
t
HIGH
See I2C Interface Timing Diagram
0.6
–
–
μs
Data Setup Time
t
SU:DAT
See note1; I2C Interface Timing Diagram
100
–
–
ns
Data Hold Time
t
HD:DAT
See I2C Interface Timing Diagram
0
–
900
ns
Setup Time for Stop Condition
t
SU:STO
See I2C Interface Timing Diagram
0.6
–
–
μs
Continued on next page



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