AD9628

Data Sheet

Rev. C | Page 6 of 42

AD9628-105

AD9628-125

Temp

Min

Typ

Max

Min

Typ

Max

Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

25°C

92

92

dBc

25°C

90

90

dBc

25°C

90

93

dBc

Full

82

85

dBc

25°C

89

90

dBc

25°C

83

84

dBc

WORST OTHER (HARMONIC OR SPUR)

25°C

−96

−94

dBc

25°C

−95

−94

dBc

25°C

−95

−95

dBc

Full

−87

−87

dBc

25°C

−93

−92

dBc

25°C

−92

−91

dBc

TWO-TONE SFDR

25°C

85

85

dBc

Full

−95

−95

dB

ANALOG INPUT BANDWIDTH

25°C

650

650

MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 3.

AD9628-105/AD9628-125

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.3

3.6

V p-p

Input Voltage Range

Full

AGND − 0.3

AVDD + 0.2

V

Input Common-Mode Range

Full

0.9

1.4

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

−10

+10

µA

Input Capacitance

Full

4

pF

Input Resistance

Full

8

10

12

kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

40

132

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT (SCLK/DFS/SYNC)2

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current (VIN = 1.8 V)

Full

−92

−135

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF