AD9628 datasheet(4/43 Pages) AD

4 / 43 page

Data Sheet

AD9628

Rev. C | Page 3 of 42

GENERAL DESCRIPTION

The AD9628 is a monolithic, dual-channel, 1.8 V supply, 12-bit,

125 MSPS/105 MSPS analog-to-digital converter (ADC). It

features a high performance sample-and-hold circuit and on-

chip voltage reference.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 12-bit accuracy at

125 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

A differential clock input controls all internal conversion cycles.

An optional duty cycle stabilizer (DCS) compensates for wide

variations in the clock duty cycle while maintaining excellent

overall ADC performance.

The digital output data is presented in offset binary, Gray code, or

twos complement format. A data output clock (DCO) is provided

for each ADC channel to ensure proper latch timing with receiving

logic. 1.8 V CMOS or LVDS output logic levels are supported.

Output data can also be multiplexed onto a single output bus.

The AD9628 is available in a 64-lead RoHS-compliant LFCSP

and is specified over the industrial temperature range (−40°C to

+85°C).

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