AD4010 datasheet(35/36 Pages) AD

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Preliminary Technical Data

AD4002/AD4006/AD4010

Rev. PrA | Page 35 of 36

LAYOUT GUIDELINES

The PCB that houses the AD4002/AD4006/AD4010 must be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. The pinout of the

AD4002/AD4006/AD4010, with its analog signals on the left

side and its digital signals on the right side, eases this task.

Avoid running digital lines under the device because they

couple noise onto the die, unless a ground plane under the

AD4002/AD4006/AD4010 is used as a shield. Fast switching

signals, such as CNV or clocks, must not run near analog signal

paths. Avoid crossover of digital and analog signals.

At least one ground plane must be used. It can be common or

split between the digital and analog sections. In the latter case,

join the planes underneath the AD4002/AD4006/AD4010

devices.

The AD4002/AD4006/AD4010 voltage reference input (REF)

has a dynamic input impedance. Decouple the REF pin with

minimal parasitic inductances by placing the reference

decoupling ceramic capacitor close to (ideally right up against)

the REF and GND pins and connect them with wide, low

impedance traces.

Finally, decouple the VDD and VIO power supplies of the

AD4002/AD4006/AD4010 with ceramic capacitors, typically

0.1 μF, placed close to the AD4002/AD4006/AD4010 and

connected using short, wide traces to provide low impedance

paths and to reduce the effect of glitches on the power supply

lines.

An example of the AD4002 layout following these rules is

shown in Figure 64 and Figure 65. Note that the AD4006/

AD4010 layout is equivalent to the AD4002 layout.

EVALUATING THE AD4002/AD4006/AD4010

PERFORMANCE

Other recommended layouts for the AD4002/AD4006/AD4010

are outlined in the user guide of the evaluation board for the

AD4002 (EVAL-AD4002FMCZ). The evaluation board package

includes a fully assembled and tested evaluation board with the

AD4002, documentation, and software for controlling the board

from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4002FMCZ

can also be used to evaluate the AD4006/AD4010 by limiting the

throughput to 1 MSPS/500 kSPS in its software (see UG-1042).

Figure 64. Example Layout of the AD4002 (Top Layer)

Figure 65. Example Layout of the AD4002 (Bottom Layer)

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