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TPA3136D2PWPR bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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TPA3136D2PWPR bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 35 page ![]() 12 TPA3136D2, TPA3136AD2 SLOS938D – MAY 2016 – REVISED MARCH 2017 www.ti.com Product Folder Links: TPA3136D2 TPA3136AD2 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 9.3 Feature Description 9.3.1 Fixed Analog Gain The analog gain of the TPA3136D2/TPA3136AD2 is fixed to 26 dB. 9.3.2 SD Operation The TPA3136D2/TPA3136AD2 device employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input pin should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage. 9.3.3 PLIMIT The PLIMIT operation will, if selected, limit the output voltage level to a voltage level below the supply rail. In this case the amplifier operates as if it was powered by a lower supply voltage, and thereby limiting the output power by voltage clipping. PLIMIT threshold is set by the PLIMIT pin voltage. Figure 16. PLIMIT Circuit Operation The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. |
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