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TPA3136D2, TPA3136AD2
www.ti.com
SLOS938D – MAY 2016 – REVISED MARCH 2017
Product Folder Links: TPA3136D2 TPA3136AD2
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
(3)
The TPA3136D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply voltage
AVCC to GND, PVCC to GND
–0.3
16
V
Input current
To any pin except supply pins
10
mA
Voltage
SD, FAULT to GND(2)
–0.3
AVCC + 0.3
V
10
V/ms
Voltage
RINN, RINP, LINN, LINP
–0.3
6.3
V
Minimum load resistance, RL
BTL, PVCC > 12 V
4.8
Ω
BTL, PVCC
≤ 12 V
3.2
PBTL, PVCC > 12 V
2.5
PBTL, PVCC
≤ 12 V
1.8
Continuous total power dissipation
See the Thermal Information Table
Operating free-air temperature range, TA
(3)
–40
85
°C
Temperature range
–65
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE
UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±250
(1)
The TPA3136D2/TPA3136AD2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must
be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN MAX
UNIT
VCC
Supply voltage
PVCC, AVCC
TPA3136
4.5
14.4
V
TPA3136A
8
14.4
VIH
High-level input voltage
SD, PBTL
2
AVC
C
V
VIL
Low-level input voltage
SD, PBTL
0.8
V
VOL
Low-level output voltage
FAULT, RPULL-UP=100 k, PVCC=14.4 V
0.8
V
IIH
High-level input current
SD, PBTL, VI = 2 V, AVCC = 12 V
50
µA
IIL
Low-level input current
SD, PBTL, VI = 0.8 V, AVCC = 12 V
5
µA
TA
Operating free-air
temperature(1)
–40
85
°C
TJ
Operating junction
temperature(1)
-40
150
°C



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