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TAS5755MDFDR bảng dữ liệu(PDF) 10 Page - Texas Instruments

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tên linh kiện TAS5755MDFDR
Giải thích chi tiết về linh kiện  2 x 50-W or 2 x 19-W1 x 50-W Digital Input Audio Amplifier With Equalizer, 2- Band DRC, And License-Free 3D Effect
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TAS5755MDFDR bảng dữ liệu(HTML) 10 Page - Texas Instruments

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10
TAS5755M
SLOS982 – AUGUST 2017
www.ti.com
Product Folder Links: TAS5755M
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
7.10 Timing Requirements - PLL Input Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fMCLKI
MCLK frequency
2.8224
24.576
MHz
MCLK duty cycle
40%
50%
60%
tr/tf(MCLK)
Rise/fall time for MCLK
5
ns
LRCLK allowable drift before LRCLK reset
4
MCLKs
7.11 Timing Requirements - Serial Audio Ports Slave Mode
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
CL = 30 pF
1.024
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
8
48
48
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising
edges
32
64
SCLK
edges
t(edge)
LRCLK clock edge with respect to the falling
edge of SCLK
–1/4
1/4
SCLK
period
tr/tf
Rise/fall time for SCLK/LRCLK
8
ns
7.12 Timing Requirements - I
2C Serial Control Port Operation
for I
2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
Frequency, SCL
No wait states
400
kHz
tw(H)
Pulse duration, SCL high
0.6
μs
tw(L)
Pulse duration, SCL low
1.3
μs
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
0
ns
t(buf)
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
μs
7.13 Timing Requirements - Reset (RESET)
control signal parameters over recommended operating conditions (unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
tw(RESET)
Pulse duration, RESET active
100
μs
td(I2C_ready)
Time to enable I2C
12
ms



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