TAS5755MDFDR datasheet(53/76 Pages) TI1

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TAS5755M

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SLOS982 – AUGUST 2017

Product Folder Links: TAS5755M

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(1)

Default values are in bold.

9.6.2.14 Oscillator Trim Register (0x1B)

The TAS5755M PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This

reduces system cost because an external reference is not required. Currently, TI recommends a reference

resistor value of 18.2 k

Ω (1%). This must be connected between OSC_RES and DVSSO.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

NOTE

Trim must always be run following reset of the device.

Table 17. Oscillator Trim Register (0x1B)

FUNCTION

–

Reserved(1)

–

Oscillator trim not done (read-only) (1)

–

Oscillator trim done (read only)

–

Reserved(1)

–

Select factory trim (Write a 0 to select factory trim; default is 1.)

–

Factory trim disabled(1)

–

Reserved(1)

(1)

This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.

(2)

Default values are in bold.

9.6.2.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset stopping all

PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 18 before attempting

to re-start the power stage.

Table 18. BKND_ERR Register (0x1C)(1)

FUNCTION

Reserved

–

Set back-end reset period to 299 ms(2)

–

Set back-end reset period to 449 ms

–

Set back-end reset period to 598 ms

–

Set back-end reset period to 748 ms

–

Set back-end reset period to 898 ms

–

Set back-end reset period to 1047 ms

–

Set back-end reset period to 1197 ms

–

Set back-end reset period to 1346 ms

–

Set back-end reset period to 1496 ms

–

Set back-end reset period to 1496 ms

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