LAN91C100FD datasheet(33/68 Pages) SMSC

33 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 33

Rev. 05/31/2000

The TX EMPTY INT ENABLE should only be set after the following steps:

a) a packet is enqueued for transmission

b) the previous empty condition is cleared (acknowledged)

TX INT - Set when at least one packet transmission was completed. The first packet number to be serviced can be read

from the FIFO PORTS register. The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS

register. After servicing a packet number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with

the TX INT bit set.

RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO

PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register.

ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of bytes received

into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch). ERCV INT stays set until

acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set.

Note: If the driver uses AUTO RELEASE mode it should enable TX EMPTY INT as well as TX INT. TX EMPTY INT will be

set when the complete sequence of packets is transmitted. TX INT will be set if the sequence stops due to a fatal error on

any of the packets in the sequence.

FIGURE 5 -

INTERRUPT

STRUCTURE

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