IRCC datasheet(67/79 Pages) SMSC

67 / 79 page

the five bytes written to the FIFO following the

second service request was not enough data to

exceed the FIFO Threshold given the long

interrupt latency.

DMA

The DMA channel works in Single-Byte and

Burst (Demand) Mode. AEN is high during DMA

transfers. The DMA controls are located in SCE

Configuration Register B.

When the DMA

Enable bit (D0) is one, DMA is enabled. The

DMA Burst Mode bit (D1) controls the DMA

mode. DRQ is further gated by the SCE Modes

bits; e.g., DRQ can only be enabled if either

Transmit or Receive mode has been enabled.

During transmit DRQ remains active as long as

the FIFO is not full until TC. During receive DRQ

remains active as long as the FIFO is not empty

until TC.

Single-Byte Mode

Single-Byte mode is enabled by resetting the

DMA Burst bit in SCE Configuration Register B.

Single-Byte DMA transfers one data byte for

each DRQ (Figure 36). Terminal Count occurs

only once, during the last byte of data block.

FIFO Int. Enable

FIFO Interrupt

Service Req.

Satisfied

Data Bytes in FIFO 51 50 49 54 ... 51 50 49 48 47 46 45 44 49 48 ...

Serv. Req. Satisfied

(long int. latency)

1st Service

Request

2nd Service

Request

3rd Service

Request

TxServReq

FIGURE 35 - FIFO INTERRUPT EXAMPLE

DMA Enable

DRQ

I/Ox

nDACK

DMA Burst

AEN

FIGURE 36 - DMA SINGLE-BYTE MODE TIMING

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