IRCC datasheet(64/79 Pages) SMSC

64 / 79 page

Initialization

The FIFO must be loaded with the appropriate

transmit data while the Block Control bits in SCE

Configuration Register A are set to the required

transfer mode with the SCE MODES bits set to

Transmit/Receive Disabled. Enough room must

remain in the FIFO for receive data.

The

Loopback Transmit CRC bit (D6) in SCE

Configuration Register B must be initialized for

the appropriate CRC response during loopback

testing.

The Data Size registers must be

properly initialized to constrain the loopback

function so that received data is not re-

transmitted. The Rx Data Size register is

required for Consumer IR Loopback tests and

the Tx Data Size register is required for IrDA FIR

Loopback tests. The RX Data Size register must

be programmed with one less than the total

number of bytes in the CIR loopback test; i.e.,

Test_byte_count_1. Proper programming of the

Tx Data Size register depends upon the state of

the CRC Select and Loopback Tx CRC bits. The

FIFO Threshold is not used for loopback tests.

The Tx Polarity and Rx Polarity bits must be the

same state for loopback tests. Set the Loopback

bit in SCE Configuration Register B to begin the

loopback test.

Retrieving Results

The loopback test data can be read from the

FIFO immediately following the End-of-Message;

i.e., the Loopback bit does not need to be reset,

nor does the FIFO need to be explicitly re-

configured for ISA bus access.

IRCC bảng dữ liệu(PDF) 64 Page - SMSC Corporation