BQ40Z50-R2 datasheet(41/51 Pages) TI1

tên linh kiện	BQ40Z50-R2

Giải thích chi tiết về linh kiện	1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager

PDF	51 Pages

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CHARGE

AND

DISCHARGE

PATH

CURRENT

FILTER

SENSE

RESISTOR

LEVEL

PROTECTOR

LEDS

THERMISTORS

Pack+

Pack±

BAT+

BAT±

Low Level Circuits

bq40z50-R2

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SLUSCS4 – JUNE 2017

Product Folder Links: bq40z50-R2

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Layout Guidelines (continued)

11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors

Use wide copper traces to lower the inductance of the bypass capacitor circuit. Figure 47 shows an example

layout, demonstrating this technique.

Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3

11.1.2 ESD Spark Gap

Protect SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The

pattern in Figure 48 is recommended, with 0.2-mm spacing between the points.

Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

11.2 Layout Example

Figure 49. Top Layer

BQ40Z50-R2 bảng dữ liệu(PDF) 41 Page - Texas Instruments