BQ40Z50-R2 datasheet(36/51 Pages) TI1

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bq40z50-R2

SLUSCS4 – JUNE 2017

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Figure 33. bq40z50-R2 PACK and FET Control

The N-channel charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a

switching time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of

an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a

reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the

PACK+ input becomes slightly negative.

Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the

FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002

as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq40z50-R2

device has the capability to provide a current-limited charging path typically used for low battery voltage or low

temperature charging. The bq40z50-R2 device uses an external P-channel, pre-charge FET controlled by PCHG.

9.2.2.3.4

Temperature Output

For the bq40z50-R2 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin

can be enabled with an integrated 18-k

Ω (typical) linearization pullup resistor to support the use of a 10-kΩ at

25°C (103) NTC external thermistor such as a Mitsubishi BN35-3H103. The reference design includes four 10-k

Ω

thermistors: RT2, RT3, RT4, and RT5. The bq40z50-R2 device supports up to four external thermistors. Connect

unused thermistor pins to VSS.

BQ40Z50-R2 bảng dữ liệu(PDF) 36 Page - Texas Instruments