S3A3 datasheet(111/139 Pages) RENESAS

111 / 139 page

R01DS0307EU0100 Rev.1.00

Page 111 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.9

POR and LVD Characteristics

Note 1.

These characteristics apply when noise is not superimposed on the power supply. When a setting causes this voltage detection

level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or LVD2 is used for voltage

detection.

Note 2.

# in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.

Note 3.

# in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.

Note 4.

# in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.

Table 2.62

Power-on reset circuit and voltage detection circuit characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Voltage detection

level*1

Power-on reset (POR)

VPOR

1.27

1.42

1.57

Figure 2.84,

Figure 2.85

Voltage detection circuit (LVD0)*2

Vdet0_0

3.68

3.85

4.00

Figure 2.86

At falling edge

VCC

Vdet0_1

2.68

2.85

2.96

Vdet0_2

2.38

2.53

2.64

Vdet0_3

1.78

1.90

2.02

Vdet0_4

1.60

1.69

1.82

Voltage detection circuit (LVD1)*3

Vdet1_0

4.13

4.29

4.45

Figure 2.87

At falling edge

VCC

Vdet1_1

3.98

4.16

4.30

Vdet1_2

3.86

4.03

4.18

Vdet1_3

3.68

3.86

4.00

Vdet1_4

2.98

3.10

3.22

Vdet1_5

2.89

3.00

3.11

Vdet1_6

2.79

2.90

3.01

Vdet1_7

2.68

2.79

2.90

Vdet1_8

2.58

2.68

2.78

Vdet1_9

2.48

2.58

2.68

Vdet1_A

2.38

2.48

2.58

Vdet1_B

2.10

2.20

2.30

Vdet1_C

1.84

1.96

2.05

Vdet1_D

1.74

1.86

1.95

Vdet1_E

1.63

1.75

1.84

Vdet1_F

1.60

1.65

1.73

Voltage detection circuit (LVD2)*4

Vdet2_0

4.11

4.31

4.48

Figure 2.88

At falling edge

VCC

Vdet2_1

3.97

4.17

4.34

Vdet2_2

3.83

4.03

4.20

Vdet2_3

3.64

3.84

4.01

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