S3A3 datasheet(47/139 Pages) RENESAS

47 / 139 page

R01DS0307EU0100 Rev.1.00

Page 47 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

2.2.9

Operating and Standby Current

Table 2.11

Operating and standby current (1) (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Typ*10

Max

Unit

Test

conditions

Supply

current

High-speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 48 MHz

ICC

8.4

ICLK = 32 MHz

5.9

ICLK = 16 MHz

3.5

ICLK = 8 MHz

2.3

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 48 MHz

17.9

ICLK = 32 MHz

12.4

ICLK = 16 MHz

7.0

ICLK = 8 MHz

4.3

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 48 MHz

21.2

ICLK = 32 MHz

16.0

ICLK = 16 MHz

8.8

ICLK = 8 MHz

5.1

All peripheral clock

enabled, code executing

from SRAM

ICLK = 48 MHz

56.0

Sleep mode

All peripheral clock

disabled

ICLK = 48 MHz

3.7

ICLK = 32 MHz

2.7

ICLK = 16 MHz

2.0

ICLK = 8 MHz

1.5

All peripheral clock

enabled

ICLK = 48 MHz

16.4

ICLK = 32 MHz

12.7

ICLK = 16 MHz

7.2

ICLK = 8 MHz

4.3

Increase during BGO operation

2.5

Middle-speed

mode

Normal mode

All peripheral clock

disabled, while (1) code

executing from flash

ICLK = 12 MHz

ICC

2.5

ICLK = 8 MHz

2.1

ICLK = 1 MHz

1.0

All peripheral clock

disabled, CoreMark code

executing from flash

ICLK = 12 MHz

5.2

ICLK = 8 MHz

4.0

ICLK = 1 MHz

1.3

All peripheral clock

enabled, while (1) code

executing from flash

ICLK = 12 MHz

6.5

ICLK = 8 MHz

4.8

ICLK = 1 MHz

1.6

All peripheral clock

enabled, code executing

from SRAM

ICLK = 12 MHz

23.0

Sleep mode

All peripheral clock

disabled

ICLK = 12 MHz

1.4

ICLK = 8 MHz

1.3

ICLK = 1 MHz

0.9

All peripheral clock

enabled

ICLK = 12 MHz

5.3

ICLK = 8 MHz

4.0

ICLK = 1 MHz

1.5

Increase during BGO operation

2.5

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