S3A3 datasheet(82/139 Pages) RENESAS

82 / 139 page

R01DS0307EU0100 Rev.1.00

Page 82 of 139

Mar 7, 2017

S3A3

2. Electrical Characteristics

Figure 2.59

SCI simple SPI mode timing (slave, CKPH = 0)

Note 1.

tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits. tPcyc: PCLKB cycle.

Note 2.

Cb indicates the total capacity of the bus line.

Table 2.39

SCI timing (3)

Conditions: VCC = 2.7 to 5.5 V

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

tSr

1000

Figure 2.60

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc*1

Data input setup time

tSDAS

250

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*2

400

Simple IIC

(Fast mode)

SDA input rise time

tSr

300

Figure 2.60

For all ports

except P408, use

PmnPFS.DSCR

of middle drive.

For port P408,

use

PmnPFS.DSCR1

/DSCR of middle

drive for IIC

fast-mode.

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc*1

Data input setup time

tSDAS

100

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*2

400

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SSn

input

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

MISOn

output

MOSIn

input

(n = 0 to 4, 9)

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