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TMS29LF040 bảng dữ liệu(PDF) 17 Page - Texas Instruments

tên linh kiện TMS29LF040
Giải thích chi tiết về linh kiện  524288 BY 8-BIT FLASH MEMORIES
PDF  38 Pages
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TMS29LF040 bảng dữ liệu(HTML) 17 Page - Texas Instruments

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TMS29LF040, TMS29VF040
524288 BY 8-BIT
FLASH MEMORIES
SMJS825D – SEPTEMBER 1995 – REVISED JUNE 1998
17
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
timing requirements controlled by E (see Figure 5)
ALTERNATE
SYMBOL
’29LF040-80
’29LF040-90
’29LF040-10
’29VF040-10
UNIT
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tAVAV
Cycle time, write
tc(W)
80
90
100
ns
tEHEH1
Cycle time, programming
operation
20
20
20
µs
tEHEH2
Cycle time, sector-erase
operation (see Note 9)
2
30
2
30
2
30
s
tEHEH3
Cycle time, chip-erase
operation (see Note 10)
14
120
14
120
14
120
s
tELAX
Hold time, address
th(A)
45
45
45
ns
tEHDX
Hold time, data
th(D)
0
0
0
ns
tEHWH
Hold time, W
th(W)
0
0
0
ns
tELEH
Pulse duration, E low
tw(EL)
35
45
45
ns
tEHEL
Pulse duration, E high
tw(EH)
20
20
20
ns
tGHEL
Recovery time, read
before write
trec(R)
0
0
0
ns
tAVEL
Setup time, address
tsu(A)
0
0
0
ns
tDVEH
Setup time, data
tsu(D)
35
45
45
ns
tWLEL
Setup time, W
tsu(W)
0
0
0
ns
ALTERNATE
SYMBOL
’29LF040-12
’29VF040-12
’29LF040-15
’29VF040-15
UNIT
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
tAVAV
Cycle time, write
tc(W)
120
150
ns
tEHEH1
Cycle time, programming operation
20
20
µs
tEHEH2
Cycle time, sector-erase operation (see Note 9)
2
30
2
30
s
tEHEH3
Cycle time, chip-erase operation (see Note 10)
14
120
14
120
s
tELAX
Hold time, address
th(A)
50
50
ns
tEHDX
Hold time, data
th(D)
0
0
ns
tEHWH
Hold time, W
th(W)
0
0
ns
tELEH
Pulse duration, E low
tw(EL)
50
50
ns
tEHEL
Pulse duration, E high
tw(EH)
20
20
ns
tGHEL
Recovery time, read before write
trec(R)
0
0
ns
tAVEL
Setup time, address
tsu(A)
0
0
ns
tDVEH
Setup time, data
tsu(D)
50
50
ns
tWLEL
Setup time, W
tsu(W)
0
0
ns
NOTES:
9. Timing diagram of E-controlled sector-erase operation not enclosed.
10. Timing diagram of E-controlled chip-erase operation not enclosed.



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