TMS29LF040 datasheet(6/38 Pages) TI

6 / 38 page

TMS29LF040, TMS29VF040

524288 BY 8-BIT

FLASH MEMORIES

SMJS825D – SEPTEMBER 1995 – REVISED JUNE 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

algorithm selection mode

The algorithm-selection mode provides access to a binary code that matches the device with its proper

programming- and erase-command operations. This mode is activated when VID (11.5 V to 12.5 V) is placed

on address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling the

address pin A0 from VIL to VIH. All other address pins can be logic low or logic high.

The algorithm-selection code also can be read by using the command register, which is useful when VID is not

available to be placed on address pin A9. Table 2 lists the binary algorithm-selection codes for the

TMS29xF040.

Table 2. Algorithm-Selection Codes†

ALGORITHM SELECTION

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

Byte 0

97h

Byte 1

94h

† A1 = VIL, A6 = VIL, E = VIL, G = VIL

erasure and programming

Erasure and programming of the TMS29xF040 are accomplished by writing a sequence of commands using

standard microprocessor write timings. The commands are written to a command register and input to the

command-state machine (CSM). The CSM interprets the command entered and initiates program, erase,

suspend, and resume operations as instructed. The CSM acts as the interface between the write-state machine

(WSM) and the external chip operations. The WSM controls all voltage

generation, pulse generation,

preconditioning, and verification of the memory contents. Program and sector/chip-erase functions are fully

automatic. When the end of a program or erase operation is reached, the device internally resets to the read

mode. If a byte-program or chip-erase operation is in progress, additional program/erase commands are

ignored until the operation in progress is completed.

command definitions

Device operating modes are selected by writing specific address and data sequences into the command

them in the incorrect sequence causes the device to reset to the read mode. The command register does not

occupy an addressable memory location. The register stores the command sequence along with the address

and data needed by the memory array. Commands are written by setting E = VIL and G = VIH and bringing W

from VIH to VIL. Addresses are latched on the falling edge of W and data is latched on the rising edge of W.

Holding W = VIL and toggling E is an alternative method. See the byte-program and chip/sector-erase sections

for a more complete description.

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