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ICS84427CMLF bảng dữ liệu(PDF) 11 Page - Integrated Device Technology

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REVISION B 5/6/15
84427 DATA SHEET
11
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 84427.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 84427 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)
MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (300mA + 30mA) = 1143.45mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj =
θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.143W * 43°C/W = 119.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE
θJA FOR 24-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
43°C/W
38°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.



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