ICS84427CMLF datasheet(9/16 Pages) IDT

9 / 16 page

REVISION B 5/6/15

84427 DATA SHEET

CRYSTAL-TO-LVDS

INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4. In a 100

Ω dif-

ferential transmission line environment, LVDS drivers require

a matched load termination of 100

Ω across near the receiver

100 Ohm Differiential Transmission Line

100

3.3V

LVDS_Driv er

3.3V

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION

input. For a multiple LVDS outputs buffer, if only partial outputs

are used, it is recommended to terminate the un-used outputs.

FIGURE 5A. 84427 SCHEMATIC EXAMPLE

SCHEMATIC EXAMPLE

Figure 5A shows a schematic example of using an 84427. In

this example, the input is a 25MHz parallel resonant crystal with

load capacitor CL=18pF. The frequency ﬁne tuning capacitors

C1 and C2 is 22pF and 18pF respectively. This example also

shows logic control input handling. The conﬁguration is set at

F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.

It is recommended to have one decouple capacitor per power

pin. Each decoupling capacitor should be located as close as

possible to the power pin. The low pass ﬁlter R7, C11 and C16

for clean analog supply should also be located as close to the

VDDA pin as possible.

F_SEL0

VDD

0.1u

F_SEL2

VDDA

VDD

LVDS_input

RD3

VDD

VDD=3.3V

VDD

F_SEL1

C11

0.1u

18p

(U1,16)

VDD

0.1u

100

VDD

RU2

SP = Spare, Not Installed

(U1,24)

Zo = 50

F_SEL0

(U1,13)

C16

10u

RU3

e.g. F_SEL[2:0]=101

Zo = 50

25MHz,18pF

F_SEL2

0.1u

ICS84427

nQ0

nQ1

nQ2

nQ3

nQ4

nQ5

VDD

VEE

PLL_SEL

VDD

VDDA

F_SEL2

XTAL_OUT

XTAL_IN

F_SEL1

F_SEL0

VDD

RD1

F_SEL1

RU1

RD2

22p

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