STM32F769AI datasheet(153/255 Pages) STMICROELECTRONICS

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DocID029041 Rev 4

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

224

TCLK-POST

Time that the transmitter

continues to send HS clock

after the last associated Data

Lane has transitioned to LP

Mode.

62+52*UI

TCLK-TRAIL

Time that the transmitter drives

the HS-0 state after the last

payload clock bit of an HS

transmission burst.

-60

THS-PREPARE

Time that the transmitter drives

the Data Lane LP-00 Line state

immediately before the HS-0

Line state starting the HS

transmission.

40+4*UI

85+6*UI

THS-PREPARE

THS-ZERO

THS-PREPARE+ Time that the

transmitter drives the HS-0

state prior to transmitting the

Sync sequence.

145+10*UI

THS-TRAIL

Time that the transmitter drives

the flipped differential state

after last payload data bit of a

HS transmission burst.

Max

(n*8*UI,

60+n*4*UI)

THS-EXIT

Time that the transmitter drives

LP-11 following a HS burst.

100

TREOT

30%-85% rise time and fall time

TEOT

Transmitted time interval from

the start of THS-TRAIL or

TCLK-TRAIL, to the start of the

LP-11 state following a HS

burst.

105+

n*12UI

1. Guaranteed based on test during characterization.

Table 52. MIPI D-PHY AC characteristics LP mode and HS/LP

transitions(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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