STM32F769AI datasheet(149/255 Pages) STMICROELECTRONICS

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

Electrical characteristics

224

5.3.12

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 61: EMI characteristics). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

MODEPER

round fPLL_IN 4fMod

()

⁄

[]

fPLL_IN and fMod must be expressed in Hz.

As an example:

tLOCK

PLLSAI lock time

VCO freq = 192 MHz

200

μs

VCO freq = 432 MHz

100

300

Jitter(3)

Master SAI clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

FS clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

400

IDD(PLLSAI)(4)

PLLSAI power consumption on

VDD

VCO freq = 192 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLSAI)(4)

PLLSAI power consumption on

VDDA

VCO freq = 192 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Table 49. PLLISAI characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 50. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.25

MODEPER * INCSTEP

215 1-

1. Guaranteed by design.

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