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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
Electrical characteristics
224
5.3.15
MIPI D-PHY regulator characteristics
The parameters given in Table 54 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 17.
IDD(PLL) PLL power consumption on VDD12
fVCO_OUT = 500 MHz
-
0.55
0.70
mA
fVCO_OUT = 600 MHz
-
0.65
0.80
fVCO_OUT = 1000 MHz
-
0.95
1.20
1. Based on test during characterization.
Table 53. DSI-PLL characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 54. DSI regulator characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD12DSI 1.2 V internal voltage on VDD12DSI
-
1.15
1.20
1.30
V
CEXT
External capacitor on VCAPDSI
-
1.1
2.2
3.3
μF
ESR
External Serial Resistor
-
0
25
600
IDDDSIREG Regulator power consumption
-
100
120
125
μA
IDDDSI
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
Ultra Low Power Mode
(Reg. ON + PLL OFF)
-
290
600
μA
Stop State
(Reg. ON + PLL OFF)
-
290
600
IDDDSILP
DSI system current consumption on
VDDDSI in LP mode communication(2)
10 MHz escape clock
(Reg. ON + PLL OFF)
-
4.3
5.0
mA
20 MHz escape clock
(Reg. ON + PLL OFF)
-
4.3
5.0
IDDDSIHS
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode communication(3)
300 Mbps - 1 data lane
(Reg. ON + PLL ON)
-
8.0
8.8
mA
300 Mbps - 2data lane
(Reg. ON + PLL ON)
-
11.4
12.5
500 Mbps - 1 data lane
(Reg. ON + PLL ON)
-
13.5
14.7
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-
18.0
19.6
DSI system (regulator, PLL and
D-PHY) current consumption on VDDDSI
in HS mode with CLK like payload
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-
21.4
23.3
tWAKEUP Startup delay
CEXT = 2.2 μF-
110
-
μs
CEXT = 3.3 μF
-
-
160
IINRUSH
Inrush current on VDDDSI
External capacitor load at start
-
60
200
mA
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.



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