STM32F102xx datasheet(23/41 Pages) STMICROELECTRONICS

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STM32F10xx8 STM32F10xxB

STM32F10xx8 and STM32F10xxB silicon limitations

Sequence 2

BTF = 1 (Data N-2 in DR and Data N-1 in shift register)

Program ACK = 0

Configure SCL I/O as GPIO open-drain output low

Read Data N-2 in DR.

Program STOP = 1,

Read Data N-1.

Configure SCL I/O as Alternate Function open drain

•

Workaround 2

Mask all active interrupts between the SET STOP and the READ data N-1 for

sequence 1; and between the READ data N-2, the SET STOP and the READ data N-1

for Sequence 2.

•

Workaround 3

Manage I2C RxNE events with DMA or interrupts with the highest priority level, so that

the condition BTF = 1 never occurs.

2.13.3

SMBus standard not fully supported

Description

The I2C peripheral is not fully compliant with the SMBus v2.0 standard since It does not

support the capability to NACK an invalid byte/command.

Workarounds

A higher-level mechanism should be used to verify that a write operation is being performed

correctly at the target device, such as:

Using the SMBAL pin if supported by the host

the alert response address (ARA) protocol

the Host notify protocol

2.13.4

Wrong behavior of I2C peripheral in master mode after a misplaced

Stop

Description

If a misplaced Stop is generated on the bus, the peripheral cannot enter master mode

properly:

•

If a void message is received (START condition immediately followed by a STOP): the

BERR (bus error) flag is not set, and the I2C peripheral is not able to send a start

condition on the bus after the write to the START bit in the I2C_CR2 register.

•

In the other cases of a misplaced STOP, the BERR flag is set. If the START bit is

already set in I2C_CR2, the START condition is not correctly generated on the bus and

can create bus errors.

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