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STM32F102xx bảng dữ liệu(PDF) 7 Page - STMicroelectronics

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STM32F10xx8 STM32F10xxB
ARM® 32-bit Cortex®-M3 limitations
1
ARM® 32-bit Cortex®-M3 limitations
An errata notice of the STM32F10xxx core is available from the following web address:
http://infocenter.arm.com.
All the described limitations are minor and related to the revision r1p1-01rel0 of the Cortex-
M3 core. Table 3 summarizes these limitations and their implications on the behavior of
medium-density STM32F10xxx devices.
Table 3. Cortex-M3 core limitations and impact on microcontroller behavior
ARM ID
ARM
category
ARM
summary of errata
Impact on
medium-density
STM32F10xxx
devices
752419
Cat 2
Interrupted loads to SP can cause erroneous behavior
Minor
740455
Cat 2
SVC and BusFault/MemManage may occur out of order
Minor
602117
Cat 2
LDRD with base in list may result in incorrect base register
when interrupted or faulted
Minor
563915
Cat 2
Event register is not set by interrupts and debug
Minor
531064
impl
SWJ-DP missing POR reset sync
No
511864
Cat 3
Cortex-M3 may fetch instructions using incorrect privilege
on return from an exception
No
532314
Cat 3
DWT CPI counter increments during sleep
No
538714
Cat 3
Cortex-M3 TPIU clock domain crossing
No
548721
Cat 3
Internal write buffer could be active whilst asleep
No
463763
Cat 3
BKPT in debug monitor mode can cause DFSR mismatch
Minor
463764
Cat 3
Core may freeze for SLEEPONEXIT single instruction ISR
Minor
463769
Cat 3
Unaligned MPU fault during a write may cause the wrong
data to be written to a successful first access
No



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