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STM32F102xx bảng dữ liệu(PDF) 20 Page - STMicroelectronics

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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32F102xx bảng dữ liệu(HTML) 20 Page - STMicroelectronics

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STM32F10xx8 and STM32F10xxB silicon limitations
STM32F10xx8 STM32F10xxB
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DocID14574 Rev 13
However, the boundary scan TAP shifts out the latest value loaded into the instruction
register, which could be “00”, “01”, “10” or “11”.
Workaround
The data shifted out, after the capture IR state, in the boundary scan flow should therefore
be ignored and the software should check not only the two least significant bits (XXX01) but
all register bits (XXXXX).
2.12
Flash memory BSY bit delay versus STRT bit setting
Description
When the STRT bit in the Flash memory control register is set (to launch an erase
operation), the BSY bit in the Flash memory status register goes high one cycle later.
Therefore, if the FLASH_SR register is read immediately after the FLASH_CR register is
written (STRT bit set), the BSY bit is read as 0.
Workaround
Read the BSY bit at least one cycle after setting the STRT bit.



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