A5975AD datasheet(22/50 Pages) STMICROELECTRONICS

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Closing the loop

A5975AD

22/50

Doc ID 018761 Rev 1

Similarly for ALC the poles can usually be defined as a double pole whose value is:

Equation 11

7.3

PWM comparator

The PWM gain is given by the following formula:

Equation 12

where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the

minimum value. A voltage feed-forward is implemented to ensure a constant GPWM. This is

obtained by generating a sawtooth waveform directly proportional to the input voltage VCC.

Equation 13

where K is equal to 0.038. Therefore the PWM gain is also equal to:

Equation 14

This means that even if the input voltage changes, the error amplifier does not change its

value to keep the loop in regulation, therefore ensuring a better line regulation and line

transient response.

In summary, the open loop gain can be expressed as:

Equation 15

Example:

Considering RC = 4.7 kΩ, CC = 22 nF and CP = 150 pF, the poles and zeroes of A0 are:

FP1 = 9 Hz

FP2 = 220 kHz

FZ1 = 1.6 kHz

If L = 10 µH, COUT = 330 µF and ESR = 25 mΩ, the poles and zeroes of ALC become:

FPLC = 2.8 kHz

FZESR = 20 kHz

F0 = 44 kHz

Finally R1 = 5.6 kΩ and R2 = 3.3 kΩ.

The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12.

PLC

OUT

⋅

⋅⋅

------------------------------------------

PWM s

()

OSCMAX

OSCMIN

–

()

-------------------------------------------------------------

OSCMAX

OSCMIN

–

⋅

PWM s

()

----

const

()

PWM s

()

-------------------- A

O s

() A

⋅⋅

⋅

()

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