STCF05TBR datasheet(16/33 Pages) STMICROELECTRONICS

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I²C bus interface

STCF05

16/33

Doc ID 15257 Rev 4

8.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an

acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock

pulse. The data on the SDA line must remain stable during the HIGH period of the clock

pulse. Any change in the SDA line at this time will be interpreted as a control signal.

8.4

Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the

acknowledge clock pulse (see Figure 7). The peripheral (STCF05) that acknowledges has to

pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is

stable LOW during this clock pulse. The peripheral which has been addressed has to

generate an acknowledge pulse after the reception of each byte, otherwise the SDA line

remains at the HIGH level during the ninth clock pulse duration. In this case, the master

transmitter can generate the STOP information in order to abort the transfer. The STCF05

won't generate the acknowledge if the VI supply is below the undervoltage lockout threshold.

Figure 5.

Timing diagram on I²C bus

Figure 6.

Bit transfer

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