STCF05TBR datasheet(15/33 Pages) STMICROELECTRONICS

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STCF05

I²C bus interface

Doc ID 15257 Rev 4

15/33

I²C bus interface

Data transmission from the main microprocessor to STCF05 and vice versa takes place

through the 2 I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up

resistors to a positive supply voltage must be externally connected).

8.1

Data validity

As shown in Figure 4, the data on the SDA line must be stable during the high period of the

clock. The HIGH and LOW state of the data line can only change when the clock signal on

the SCL line is LOW.

8.2

Start and stop conditions

Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 5 a

start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop

condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition

must be sent before each START condition.

Figure 4.

Data validity on the I²C bus

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