EM351-RTR datasheet(125/241 Pages) SILABS

tên linh kiện	EM351-RTR

Giải thích chi tiết về linh kiện	High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

PDF	241 Pages

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nhà sản xuất	SILABS [Silicon Laboratories]

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Rev 1.3

Figure 9.16. Control Circuit in External Clock Mode 2

9.3.4. Capture/Compare Channels

Each capture/compare channel is built around a capture/compare register including a shadow register, an input

stage for capture with digital filter, multiplexing and prescaler, and an output stage with comparator and output

control.

Figure 9.17 gives an overview of the input stage of one capture/compare channel. The input stage samples the

corresponding TIy input to generate a filtered signal (TIyF). Then an edge detector with polarity selection generates

a signal (TIyFPy) which can be used either as trigger input by the slave mode controller or as the capture

command. It is prescaled before the capture register (ICyPS).

Figure 9.17. Capture/Compare Channel (Example: Channel 1 Input Stage)

The output stage generates an intermediate reference signal, OCyREF, which is only used internally. OCyREF is

always active high, but it may be inverted to create the output signal, OCy, that controls a GPIO output. Figure 9.18

shows the basic elements of a capture/compare channel.

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